Modelling of Symmetrical 13 Level and Asymmetrical 31 Level Generalized Cascaded Multilevel Inverters

Multi-Level Inverters (MLIs) are dealt with keen academic interest and purposeful industrial use for high-voltage applications, to meet large power demands and achieve quality output voltage. They find applications in conveyors, compressors, pumps, mills, fans, blowers, power systems, mine hoists, locomotives, and more. MLIs are crucial for the smooth operation of AC drives, UPS, railway steam locomotives, grid-connected photovoltaic systems, and have garnered interest from researchers due to their low distortion levels and production of high-quality output power compared to conventional two-level Voltage Source Inverters (VSIs). This thesis proposes a generalized MLI with a low number of switches, offering advantages like reduced harmonic distortion, increased output quality, and minimized switching and conduction losses without affecting output power. In this work, a new topology based on a cascaded connection of single-phase sub-MLI units is proposed. This topology generates positive output levels, and an H-Bridge is connected in parallel to generate negative levels. This approach treats the inverter as a generalized MLI, reducing the number of DC sources, switches, and achieving minimum THD. The cascaded inverter with multiple levels is studied in symmetric and asymmetric topologies. Symmetric topology features equal DC source values, while asymmetric topology uses different values. The proposed single-phase 7-level symmetric MLI is compared to the present H-bridge 7-level MLI in terms of total DC resources, required switches, fundamental voltage and current, and THD. The Multi-carrier Level-Shifted Sinusoidal Pulse Width Modulation (MCLSSPWM) approach is used to generate switching pulses. Later, the same single-phase proposed 13-level symmetrical MLI is compared with a 31-level asymmetrical MLI, requiring fewer switches to achieve more output levels. An optimal structure is considered with minimal switching devices, low DC voltage sources, and fewer off-state voltages on switching devices. This results in employing 12 switches with 4 DC sources to produce 31 output levels. The 31-level inverters are implemented with single-phase and extended to three-phase MLIs, utilizing the MCLSSPWM technique to produce switching pulses. The proposed model offers advantages of low THD and high fundamental voltage and current when compared to conventional H-bridge MLI. The validation of the proposed topology is verified using MATLAB/SIMULINK.