Optimization of Area and Wirelength Using Hybrid BPSO Algorithm in VLSI Floorplan and Placement for IC Design

For hierarchical, building-block design methodologies, floorplanning is a crucial physical design stage. As the size of the circuit grows, so does the intricacy of the circuitrises. To deal with the growing complexity of design, the modules for intellectual property (IP) are commonly used infloorplanning. A hybrid particle swarm is presented in this work. For floorplanning optimization, there is an optimization algorithm. Here in order to avoid overlapping, B*tree is utilized at the beginningof modules, and then the PSO algorithm, as well as the idea. The Bat Algorithm is used to generate crossover and mutationsobtain the best possible placement solution. The primary goal of floorplanning is to reduce chip area and connectionslength of wire The Microelectronics Experiment Results Benchmark circuits from the Center of North Carolina (MCNC) that our method has a higher convergence rate.