Implementation of Improved High Speed SHA-256 Algorithm from RTL to GDSII Using Verilog HDL

The Secure Hash Algorithm (SHA)—256 algorithms generates the 32 byte signature of text file. The SHA consists two main sub blocks named message scheduler, message compressor. The message scheduler and message compressor entities are enhancing the hash algorithm to reduce the critical path, area and power. The conventional SHA 256 works at 181.8 MHz frequency. The Proposed SHA-256 algorithm works at 200 MHz frequency. The optimized SHA-256 implementation achieved 10% in frequency, 14.0382% in leakage power, 33.418% in dynamic power, 33.417% improvement in total power as compared with conventional SHA-256. The synthesis is done with the help of Genus cadence tool using 45 nm technology.