VHDL Constructs

This chapter begins looking at the basic construction of a VHDL model. This chapter begins by covering the built-in features of a VHDL model including the file structure, data types, operators, and declarations. This chapter provides a foundation of VHDL that will lead to modeling examples provided in Chap. 3 . VHDL is not case sensitive. Each VHDL assignment, definition, or declaration is terminated with a semicolon (;). As such, line wraps are allowed and do not signify the end of an assignment, definition, or declaration. Line wraps can be used to make the VHDL more readable. Comments in VHDL are preceded with two dashes (i.e., --) and continue until the end of the line. All user-defined names in VHDL must start with an alphabetic letter, not a number. User-defined names are not allowed to be the same as any VHDL keyword. This chapter contains many definitions of syntax in VHDL.