Cryogenic CMOS for Quantum Computing

To fully deploy power of quantum computing (QC), practical quantum computers require the integration of a large number of qubits, e.g., in the thousands and millions, to overcome the fragility of the quantum states. Those qubits reside in extremely low temperatures (e.g., tens of mK) and demand a high degree of integration, low noise, and low power consumption for the control and read-out electronics. Following decades of technology scaling, classic CMOS has achieved extreme miniaturization with a well-established global eco-system. QC/CMOS integration is thus poised to be one the best solutions for the scalability problem for quantum computing. Although intended for applications operating well above 200K, standard CMOS technologies have been experimentally verified to perform well at cryogenic temperatures (cryo-CMOS). However, many challenges remain to enable deployment of cryo-CMOS and integration of QC/CMOS. In this chapter, we explain and address a few of such challenges, focusing on the background and progress of the device physics research. The background and progress of QC, with particular emphasis on silicon spin quantum dot (QD) and its need for QC/CMOS integration, is first introduced. Two critical aspects of the cryo-CMOS behaviors, namely transport and high-frequency noise, are then highlighted. Finally, the chapter is concluded with a brief overview on the needs and challenges of cryogenic numerical simulation tool.