Research Valorization: Radiation-Hardened ADPLL

This chapter is focused on the design and development of a radiation-hardened, wide-band, low phase-noise fractional-N all-digital phase-locked-loop (ADPLL)-based frequency synthesizer for clock and pulse-width-modulated (PWM) signal generation. The prototype of the frequency synthesizer is implemented using a commercial 65 nm CMOS technology. The synthesizer features LVDS, LVCMOS, and PWM outputs and is targeted for use in various application areas as in space, nuclear power plants, and HEP experiments, and therefore hardened with respect to both TID and SEEs (SELs, SEUs, and SETs). The project is planned, designed, and implemented as a part of an industrial collaboration between the ADVISE research group of KU Leuven and MAGICS Technologies and funded by the European Space Agency (ESA). The fully integrated ADPLL comprises a Digitally Controlled Oscillator (DCO), Multi-Modulus Divider (MMD), Time-to-Digital Converter (TDC), digital loop filter, output dividers, buffers along with several bias generating circuits, and digital communication interfaces. I contributed to this project by designing the DCO, MMD, output dividers, and output buffers.