Multi-Order Differential Delta-Sigma TDC

This chapter presents a novel differential \(\Delta \Sigma \) time-to-digital converter implemented in a 65 nm CMOS process. The 0.018 mm2 \(\Delta \Sigma \) -TDC with a maximum Trange of 98 ( \(=\pm \) 49) ns uses a time-based FIR filter in feedback to realize first, second, and third orders of \(\Delta \Sigma \) modulation. It consumes 11–15.8 μW from a 0.6 V supply and achieves the best state-of-the-art energy efficiency of 15.6–89.2 fJ/conversion step at 10 MHz clock frequency for multiple orders ( \(\le \) 3) of noise-shaping filters. This chapter is arranged as follows: Section 6.1 discusses the prior art. Section 6.2 elaborates on the architecture and explains the working principle of the proposed time-based \(\Delta \Sigma \) -TDC. Section 6.3 discusses the circuit-level implementation of the TDC in detail. The measurement setup for the TDC design is described in Sect. 6.4, and the results obtained are also analyzed and discussed to assess the performance. Section 6.5 concludes the chapter by summarizing the performance parameters of the implemented \(\Delta \Sigma \) -TDC.