Hardware–Software Co-design of Deep Neural Architectures: From FPGAs and ASICs to Computing-in-Memories

Deploying deep neural networks (DNNs) on embedded systems is a great challenge because the low-power embedded processor cannot meet the requirement for running power-hungry, computationally intensive DNNs. To address this challenge, software researchers design simpler DNNs for the existing embedded processors, and hardware designers offer more power-efficient processors to host these DNNs. By combining the efforts of both ends, software–hardware co-design targets to find a DNN model-embedded processor design pair that can offer both high DNN performance and hardware efficiency. In this chapter, we first introduce the general idea of software–hardware co-design and then showcase three lines of work targeting DNN implementation on field programmable gate arrays, application-specific integrated circuits, and compute-in-memory accelerators.