TinyVers: A Tiny Versatile All-Digital Heterogeneous Multi-core System-on-Chip

Extreme edge devices or Internet of Thing nodes require energy-efficient, ultra-low power, always-on processing, and the ability to do on-demand sampling and processing. Though field programmable gate array (FPGA)s are extremely flexible, they are neither energy-efficient nor low-power platforms. FPGAs also lack the fine-grained control to implement power management and control. Thus, this chapter transitions toward application-specific integrated circuits (ASIC) implementation to cater to the needs of (extreme) edge devices. However, this brings challenges in hardware design to build flexible processors operating in ultra-low power regimes. Flexibility in ASIC processors can be achieved through two possible solutions: (1) building reconfigurable single-core accelerators and/or (2) using multiple diverse but efficient cores in a heterogeneous setting. This chapter takes the first step in improving the flexibility of the specialized accelerators presented in the previous chapter by adding reconfigurability and also extends the flexibility by integrating this single-core accelerator in a heterogeneous multi-core system-on-chip. Toward this goal, this chapter presents TinyVers, a tiny versatile ultra-low power Machine learning (ML) system-on-chip to enable enhanced intelligence at the Extreme Edge. TinyVers exploits dataflow reconfiguration to enable multi-modal support and aggressive on-chip power management for duty cycling to enable intelligent sensing applications. The system-on-chip (SoC) combines a RISC-V host processor, a 17 tera operations per second per watt (TOPS/W) dataflow reconfigurable ML accelerator, a \(1.7\,\mu \) W deep sleep wake-up controller, and an emagneto-resistive random access memory (MRAM) for boot code and ML parameter retention. The heterogeneous multi-core SoC can perform up to 17.6 giga operations per second (GOPS) while achieving a power consumption range from \(1.7\,\mu \) W to 20 mW. Multiple ML workloads for diverse applications are mapped on the SoC to showcase its flexibility and efficiency. All the models achieve 1–2 TOPS/W of energy efficiency with power consumption below \(230\,\mu \) W in continuous operation. In a duty cycling use case for machine monitoring, this power is reduced to below \(10\,\mu \) W.