Energy-Efficient Single-Core Hardware Acceleration

This chapter deals with designing and implementing single-core specialized hardware accelerators for Machine learning (ML) applications, one abstraction level below the previous chapter. Specifically, a deep neural networks (DNN) hardware accelerator on field programmable gate array (FPGA) for object detection is used as a target application. The advantages that drive the choice of FPGA are the turnaround time of implementation and the availability of complete systems with DRAM, connectivity with a host PC, and several sensor interfaces, enabling real-time demos. The implementation is optimized based on the methodology from the hardware–software co-design concepts and the ZigZag framework to achieve high energy efficiency and throughput on the hardware for the given application.