Design-for-Testability and Its Impact on Logic Locking

The availability of access to integrated circuits’ scan chain is an inevitable requirement of modern ICs for testability/debugging purposes. However, leaving open access to the scan chain resulted in numerous security threats to ICs. It raises challenging concerns, particularly when the security assets, like secret information, are seated within the chip, such as the keys of cryptographic cores or, similarly, logic locking keys. So, to combat these threats, numerous secure scan chain architectures have been proposed in the literature to prevent any unauthorized access to the scan chain. They also keep the availability of the scan chain for testability/debugging. In this chapter, we first show why a secure scan chain architecture is required when security primitives, like logic locking, are in place. Then, we provide a holistic overview of all secure scan chain architectures starting from preliminary methods introduced when cryptography cores are in place and the adversary threat model is very limited. It is then followed by newer and more advanced methods introduced when logic locking is in place and the adversary threat model is much stronger.