Multilayer Approach to Logic Locking

The rising need to safeguard semiconductor intellectual property (IP) from untrusted entities during the design and fabrication process has spurred the development of logic locking as a promising solution. By integrating additional key gates into the circuit, logic locking obscures both the implementation details and the functional behavior of the IP. However, despite its potential, logic locking techniques have proven susceptible to various classes of attacks, including oracle-guided, oracle-less, and physical attacks. While the research community has proposed numerous countermeasures against these attacks, none of them offer absolute invulnerability against oracle-guided, oracle-less, and physical attacks simultaneously. Given this scenario, a defense-in-depth mechanism must be emerged as a viable strategy for addressing the inherent vulnerabilities of logic locking. Such an approach must implement multiple layers of independent countermeasures within the device to provide aggregated protection against different attack vectors. Introducing such a multilayered countermeasure framework in logic locking is imperative. In this chapter, our focus lies in identifying the core components of logic locking schemes that require safeguarding. Furthermore, we classify the vulnerabilities associated with these core components based on potential threats to the locking key within logic locking schemes. By doing so, we highlight the necessity of integrating different countermeasures at various layers to ensure comprehensive protection against these vulnerabilities. This chapter aims to shed light on the importance of a multilayered defense strategy and the selection of appropriate countermeasures to fortify logic locking against diverse attack vectors.