Introduction

At the time, when I started writing this book, the iPhone 13 series was being launched. And the most striking thing, for me as a researcher, is that the new-generation iPhones have been able to shrink the CMOS channel width by yet another 2 nm. They used a 5-nm technology node which allowed them to use \(27\%\) more transistors than the previous generation. Still, this progression is not too far from the quintessential Moore’s law prediction (Moore et al. (Cramming more components onto integrated circuits, 1965)). Although area scaling continues roughly at the rate of 0.5 times every two years (Bohr and Young (IEEE Micro 37(6):20–29, 2017)), the cost to build transistors and the power consumption per unit transistor have not been able to follow the promises of Moore’s law and Dennard scaling methodology (Dennard et al. (IEEE J Solid-State Circ 9(5):256–268, 1974)). This trend has not been abrupt and Moore’s law that has been guiding and predicting transistor downsizing from the last five decades is really pushing the physical limits of the transistor’s channel width, as 1 nm is equivalent to the thickness of just 5 silicon atoms!