Reducing Clock Power by Using the Clock Gating Technique

The clock signal is always a significant way of mouse and is a worst issue in any synchronous circuit. Clock gates are a successive method of minimize positive power dissolution in digital circuits. A general-purpose microprocessor is a typical synchronous circuit, which is active. To avoid unnecessary power consumption of the circuit by closing the inactive portion of the circuit. One method is to hide the pulse that drives the torpid part of the circuit. I will present a review of existing clock triggering methods as well as a comparative analysis of these clock triggering techniques on a variety of synchronous digital designs such as ALU and FIFO.