SRAM-Based In-Memory Computing: Circuits, Functions, and Applications

As the demand for data-centric applications grows, traditional Von Neumann architectures are increasingly strained. The frequent need for memory access in computing AI models and the separation of computing and storage in these architectures lead to significant inefficiencies, particularly when large amounts of data traverse multiple memory hierarchies. To address these challenges, researchers are exploring in-memory computing (IMC) and near-memory computing (NMC) architectures, which minimize data movement between processing units and storage elements, thereby alleviating the Von Neumann bottleneck. The NMC/IMC paradigm represents a promising solution, focusing on bringing logic closer to or integrating it within memory. A commercially available memory architecture, static random-access memory (SRAM), is particularly suited to this approach. SRAM is fast, stable, power-efficient, and compatible with cutting-edge technology. This chapter delves into the evolution of SRAM-based IMC technology, examining its circuit design, functionality, and application levels. We also discuss commercial SRAM-based IMC’s limitations, constraints, and future prospects. Furthermore, we explore the use of SRAM-based IMC and NMC for search, Boolean logic, and arithmetic operations, as well as its potential applications in machine learning (ML) and encryption algorithms, with a particular focus on neural networks.