On-Chip DNN Training for Direct Feedback Alignment in FeFET

The current backpropagation (BP) training algorithm for deep neural networks (DNNs) requires all trainable parameters be stored in memory and used sequentially in the backward path, which makes training parallelization extremely challenging and also incurs significant memory and computing overhead. In this chapter, we set out to address these challenges by combining innovation in training algorithm, circuit, and architecture. Specifically, we leverage the recently proposed direct feedback alignment (DFA) training algorithm to overcome the limitations of long-range data dependency required by the BP algorithm. In order to deploy DFA on hardware systems with limited resource, we propose a pipelined DNN training accelerator architecture and implement the design using ferroelectric field-effect transistors (FeFET) to take advantage of their high-performance and low-power operations. To further improve the power efficiency, we identify two architectural challenges unique to DFA-based training: a low-cost on-chip random number generator and an efficient analog-to-digital converter (ADC). We then propose a random number generator based on the statistical switching in FeFETs and an ultra-low-power FeFET-based ADC. We evaluate the proposed design against state-of-the-arts resistive memory-based DNN training accelerators. We show the proposed design achieves 1.3 × speedup and 2.5 × improvement on power efficiency.