Abstract
Some results on the miniaturization of silicon-on-insulator (SOI) structures and SOI elements of integrated circuits (IC) were presented. To increase IC performance efficiency, it was necessary to increase barriers and pulling electrical fields by means of high- \(k\) dielectrics and nanoscales, which appreciably reduced the mobility of charge carriers at a decrease in the length and width of a channel. Along with an increase in leakage due to source-drain tunnel currents, this limited the physical length of a channel by 10 nm even when silicon was replaced by two-dimensional (2D) materials, such as graphene and metals dihalcogenides. Three-dimensional (3D) integration in the form of double-gate transistors with complete depletion in the SOI structures with high- \(k\) buried dielectric (h- \(k\) BOX) in the form of so-called fin transistors (FinFET) with two to four gates all around (GAA) and channels from nanowires (NW FET), nanosheets (NS FET), and nanoforks (FS FET), 2D materials, and their 3D packing made it possible to increase the number of transistors on a chip, but not their performance efficiency. The variant considered as an alternative to improve the functionality of these elements was to replace the dielectrics in capacitors and transistors with ferroelectrics and resistors with memristors to turn from binary to neuromorphic logic and, in addition, to implement the principles of radiophotonics and quantum devices and sensors with parallel processing. The dynamically adjustable threshold and polarization of gate ferroelectrics in the complementary MOS metal-oxide-semiconductor field-effect transistors (MOS FET) of heterosystems on a chip (SoC) will retain ultralow power consumption.
