Scholarlink

<p>Metal-gate interlayer (G.IL)-ferroelectric (FE)-channel interlayer (Ch.IL)-Si (MIFIS) ferroelectric field-effect transistors (FeFETs) are attractive for large memory window (MW) and low-voltage FE NAND operation. Nevertheless, its fundamental operating principle also makes the device vulnerable to threshold voltage (V<sub>th</sub>) shift under repeated disturb bias, which remains a major obstacle to array-level reliability. In this study, we employ a TiO<sub>2</sub> nanolayer (NL) at the upper interface of the HZO FE layer to address this issue while preserving the low-voltage advantage of the MIFIS structure. The inserted TiO<sub>2</sub> modifies the interfacial electrostatics and the ferroelectric switching characteristics at the same time. First, owing to its high dielectric constant and band alignment, it facilitates additional gate-side charge storage near the G.IL/FE interface. Second, it alters the switching nature of the underlying HZO toward a more abrupt response associated with enlarged effective domain size and improved remanent polarization. The proposed device with TiO<sub>2</sub> NL operates below 15 V, while maintaining a large MW of 7.57 V, which is 18.9% higher than the reference device. Notably, the proposed device remains disturbance-free even after 10<sup>5</sup> cycles of 9 V/10 µs disturbance stress, whereas the counterpart experiences severe disturbance under the same conditions. Thus, we clarify that partial P switching acts as the primary driver of disturbances, as it precedes charge trapping and accelerates gate charge injection. Finally, while our top-interface engineering successfully optimizes gate-side dynamics, we propose that replacing the Si channel and bottom interlayer with emerging van der Waals (vdW) semiconductors and 2D insulators (e.g., h-BN) can fundamentally suppress channel-side charge injection (Q<sub>it</sub>). Combining this vdW-based bottom-interface with our TiO<sub>2</sub> top-interface strategy presents a comprehensive blueprint to expand the MW and realize ultimate disturbance-free operation in next-generation computing architectures.</p> Graphic abstract <p></p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

TiO2 nanolayer-assisted top-interface engineering for disturbance-free FeFETs: a blueprint for future van der Waals memory

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2026年5月23日

查看全文
  • Hyunjun Kang,
  • Junhyeok Kwak,
  • Giuk Kim,
  • Sangho Lee,
  • Yongyeon Kim,
  • Sanghyun Park,
  • Suhwan Lim,
  • Kwangyou Seo,
  • Wanki Kim,
  • Daewon Ha,
  • Jinho Ahn,
  • Sanghun Jeon

摘要

Metal-gate interlayer (G.IL)-ferroelectric (FE)-channel interlayer (Ch.IL)-Si (MIFIS) ferroelectric field-effect transistors (FeFETs) are attractive for large memory window (MW) and low-voltage FE NAND operation. Nevertheless, its fundamental operating principle also makes the device vulnerable to threshold voltage (Vth) shift under repeated disturb bias, which remains a major obstacle to array-level reliability. In this study, we employ a TiO2 nanolayer (NL) at the upper interface of the HZO FE layer to address this issue while preserving the low-voltage advantage of the MIFIS structure. The inserted TiO2 modifies the interfacial electrostatics and the ferroelectric switching characteristics at the same time. First, owing to its high dielectric constant and band alignment, it facilitates additional gate-side charge storage near the G.IL/FE interface. Second, it alters the switching nature of the underlying HZO toward a more abrupt response associated with enlarged effective domain size and improved remanent polarization. The proposed device with TiO2 NL operates below 15 V, while maintaining a large MW of 7.57 V, which is 18.9% higher than the reference device. Notably, the proposed device remains disturbance-free even after 105 cycles of 9 V/10 µs disturbance stress, whereas the counterpart experiences severe disturbance under the same conditions. Thus, we clarify that partial P switching acts as the primary driver of disturbances, as it precedes charge trapping and accelerates gate charge injection. Finally, while our top-interface engineering successfully optimizes gate-side dynamics, we propose that replacing the Si channel and bottom interlayer with emerging van der Waals (vdW) semiconductors and 2D insulators (e.g., h-BN) can fundamentally suppress channel-side charge injection (Qit). Combining this vdW-based bottom-interface with our TiO2 top-interface strategy presents a comprehensive blueprint to expand the MW and realize ultimate disturbance-free operation in next-generation computing architectures.

Graphic abstract