<p>Two-dimensional (2D) platinum diselenide (PtSe₂) has emerged as a promising noble-metal-based transition metal chalcogenide (TMD) for next-generation nanoelectronics due to its excellent chemical stability and favorable carrier mobility. Although defect-mediated electronic tuning is important for advancing PtSe₂-based device platforms, existing post-growth approaches, i.e., plasma and ion-based treatments, tend to cause structural damage which are not compatible with wafer-scale processing. Thermal annealing offers a more scalable and less destructive route; however, the structural, chemical, and electronic evolution of wafer-scale CVD-grown PtSe₂ under thermal treatment remains insufficiently understood. In this work, we systematically investigate wafer-scale CVD-grown PtSe₂ layers before and after post-annealing process to clarify the thermal-driven modification of their structural, optical, chemical, and electronic properties. As-prepared PtSe₂ layers exhibit uniform- and wafer scale-layered crystallinity and intrinsic <i>p</i>-type semiconducting behavior. Upon moderate annealing at 400 ℃, the PtSe₂ layers undergo a distinct transition toward metallic-like transport, revealed by reduced gate modulation, suppressed temperature-dependent conductance, and the pronounced decrease in activation energy. X-ray photoelectron spectroscopy identifies the shift toward Pt-rich, Se-deficient stoichiometry accompanied by the emergence of metallic Pt⁰ states, indicating thermally induced chalcogen-vacancy formation. Complementary optical absorbance and Tauc-plot analyses confirm bandgap narrowing and a downward shift of the Fermi level, consistent with defect-induced restructuring of the electronic band landscape. This study establishes thermal annealing as a scalable and effective route for defect-engineered modulation of PtSe₂ layers, enabling a controllable semiconductor-to-metal-like transition suitable for next-generation electronic, sensing, and contact-engineered device architectures.</p>