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<p>The first written mention of computing based on mapping of topological structures and mathematical algorithms onto graphs to be built into hardware, for graph-based computing, dates back to January 1984, when one of the authors of this text, as a Purdue University faculty member, submitted a related proposal to the Defense Department of RCA, Camden, New Jersey, USA. A preliminary study concluded that the optimal structure for mapping algorithms onto hardware is not square, but of the hexagonal shape referred to as “honeycomb”. That is how the term honeycomb was created in the context of mapping structures and algorithms onto hardware. According to the open literature the first structures ever mapped onto the honeycomb architecture are interconnection networks and the first algorithms ever mapped onto the honeycomb architecture are neural networks. If a structure or an algorithm is mapped onto a graph to be built into the hardware, conditions are met for data to flow from inputs to outputs, driven by the voltage difference between inputs and outputs. If that goal is accomplished, potentials are generated for data to move faster, which means that the algorithms get executed with a speed-up. If the data movement is accomplished with a slower clock, less energy is consumed during data propagation through structures and the execution of an algorithm. Consequently, since no control mechanisms have to be implemented, the volume of the engine becomes smaller. And finally, since the structure of the data path is formed at the time of mapping the graph into hardware, the width of the data path could be made as wide as needed, and no wider than needed, which leads to a lot better precision, at no cost in the domain of execution time. Of course, the described paradigm shift became utilizable in practice only after the reconfigurable hardware was invented. That is why the first data flow machines, based on the same or similar concept, appeared only after the FPGA circuits became widespread. However, the full utilization of this paradigm will be possible only after the Analog See of Gates circuits become feasible, which enables a lot lower operational frequency (a lot lower power consumption) and a lot higher speed (due to fewer obstacles on the data propagation paths). This article sheds light on the complexity and speed related to the mapping of structures and algorithms.</p>

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On mapping of topological structures and mathematical algorithms onto specialized architectures for graph-based computing

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2026年1月22日

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  • Veljko Milutinovic,
  • Dragana Milutinovic,
  • Borko Furht

摘要

The first written mention of computing based on mapping of topological structures and mathematical algorithms onto graphs to be built into hardware, for graph-based computing, dates back to January 1984, when one of the authors of this text, as a Purdue University faculty member, submitted a related proposal to the Defense Department of RCA, Camden, New Jersey, USA. A preliminary study concluded that the optimal structure for mapping algorithms onto hardware is not square, but of the hexagonal shape referred to as “honeycomb”. That is how the term honeycomb was created in the context of mapping structures and algorithms onto hardware. According to the open literature the first structures ever mapped onto the honeycomb architecture are interconnection networks and the first algorithms ever mapped onto the honeycomb architecture are neural networks. If a structure or an algorithm is mapped onto a graph to be built into the hardware, conditions are met for data to flow from inputs to outputs, driven by the voltage difference between inputs and outputs. If that goal is accomplished, potentials are generated for data to move faster, which means that the algorithms get executed with a speed-up. If the data movement is accomplished with a slower clock, less energy is consumed during data propagation through structures and the execution of an algorithm. Consequently, since no control mechanisms have to be implemented, the volume of the engine becomes smaller. And finally, since the structure of the data path is formed at the time of mapping the graph into hardware, the width of the data path could be made as wide as needed, and no wider than needed, which leads to a lot better precision, at no cost in the domain of execution time. Of course, the described paradigm shift became utilizable in practice only after the reconfigurable hardware was invented. That is why the first data flow machines, based on the same or similar concept, appeared only after the FPGA circuits became widespread. However, the full utilization of this paradigm will be possible only after the Analog See of Gates circuits become feasible, which enables a lot lower operational frequency (a lot lower power consumption) and a lot higher speed (due to fewer obstacles on the data propagation paths). This article sheds light on the complexity and speed related to the mapping of structures and algorithms.