Resistive Memory in 2T1R Architecture Based on Si MOSFETs and Nanocomposite Memristors

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发表日期：

2024年6月1日

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I. A. Surazhevsky,
K. Yu. Chernoglazov,
I. V. Alyaev,
Yu. V. Grischenko,
D. V. Ichyotkin,
A. V. Emelyanov,
T. E. Grigoriev,
A. D. Kalyonov,
A. I. Iliasov,
V. A. Demin,
V. V. Rylkov

摘要

A manufacturing sequence for the formation of controlled memory in the 2T1R architecture using Si MOSFETs (metal-oxide-semiconductor field-effect transistor) and memristor crossbars based on thin layers of CoFeB-LiNbO₃ nanocomposite and a-LiNbO₃ is developed. It is shown that when using Cu top electrodes in memristors, relatively small resistive-switching voltages and currents (2.5 V and 0.4 mA) are achieved, which are suitable for creating a memory microchip within the MPW technology service (https://mpw.miet.ru/).