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Abstract <p>At present, the quality and reliability problems caused by the downscaling of the process size have become a serious issue that is hindering the evolution of Moore’s law, which is manifested in the heat dissipation and leakage current caused by the short channel effect (SCE), and the drain-induced barrier lowering effect (DIBL). In this paper, the <i>I</i>-<i>V</i> transfer characteristic curves, <i>I</i>-<i>V</i> input-output curves and electrical parameters of <i>n</i>-MOSFET devices with different channel parameters of <i>W</i>/<i>L</i> are investigated by adjusting the different thickness high-κ dielectric layer of the gate stacks, such as threshold voltage (<i>V</i><sub>TH</sub>), maximum transconductance (<i>g</i><sub>m</sub>)<sub>,</sub> subthreshold swing (<i>SS</i>), drain saturation current (<i>I</i><sub>DS</sub>) and effective carrier mobility (μ<sub>eff</sub>), and so on. The results demonstrate that the double-layer gate stacks with an 8 nm TiO<sub>2</sub>/4 nm HfO<sub>2</sub> can optimize the electrical properties of <i>n</i>-MOSFET devices, such as <i>SS</i>, <i>g</i><sub>m</sub> and saturated drain current (it is &gt;20% higher than that of a single layer), mitigating the trade-off dilemma of dielectric-bandgap-thermal stability in traditional high-κ dielectric, which provides approach for optimizing MOSFETs with superior electrical performance, higher quality and reliability in the post-Moore era.</p>

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Effect of High-κ Dielectric Gate Stacks and Thickness on Electrical Performance of n-MOSFET Devices

  • 期刊论文

  • 发表日期：

    2026年1月1日

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  • Mengfan Zhang,
  • Danghui Wang,
  • Tianhan Xu,
  • Chaoyu Feng

摘要

Abstract

At present, the quality and reliability problems caused by the downscaling of the process size have become a serious issue that is hindering the evolution of Moore’s law, which is manifested in the heat dissipation and leakage current caused by the short channel effect (SCE), and the drain-induced barrier lowering effect (DIBL). In this paper, the I-V transfer characteristic curves, I-V input-output curves and electrical parameters of n-MOSFET devices with different channel parameters of W/L are investigated by adjusting the different thickness high-κ dielectric layer of the gate stacks, such as threshold voltage (VTH), maximum transconductance (gm), subthreshold swing (SS), drain saturation current (IDS) and effective carrier mobility (μeff), and so on. The results demonstrate that the double-layer gate stacks with an 8 nm TiO2/4 nm HfO2 can optimize the electrical properties of n-MOSFET devices, such as SS, gm and saturated drain current (it is >20% higher than that of a single layer), mitigating the trade-off dilemma of dielectric-bandgap-thermal stability in traditional high-κ dielectric, which provides approach for optimizing MOSFETs with superior electrical performance, higher quality and reliability in the post-Moore era.