High-Performance T-Gated GaN-HEMT on Silicon Wafer with Step Graded Strain Relief Layered-InGaN Buffer for Future Power Switching Systems
摘要
GaN-based High Electron Mobility Transistors (HEMTs) on silicon are gaining attention in RF and power electronics due to their high performance and cost-efficient production potential. This study used TCAD software to examine the DC/RF power behavior of a new strain relief layered T-gate GaN-HEMT on a Si wafer. Several factors were examined, including the work function, gate recess, gate length, length from gate-to-source (LGS), and length from gate-to-drain (LGD) scaling. The highest drain current (ID) for this structure with LG = 40 nm observed 1.98 A/mm, and the highest GM (transconductance) observed in this research work is 934.29 mS/mm. While the threshold voltage remained unchanged, the drain current, GM, and fT were all enhanced by shortening the gate length. The gate materials with higher work functions (Pt and Ir) exhibit a greater downward band bending in the conduction band near the gate region, compared to materials with lower work functions (Al and Ti). The Fermi level remains unchanged as it aligns with the device equilibrium. The observed shifts in the conduction band suggest that higher work function gate materials reduce the 2DEG density near the gate region, while lower work function materials maintain or slightly increase the density. The broad variety of applications for this device, including RF power amplifiers and high voltage devices utilized in power electronic systems, has led to its recent surge in popularity.