Abstract
The novel hetero-dielectric gate dual-source vertical tunnel field effect transistor architecture (HDG-DS-VTFET) is investigated in this paper along with an analysis of its DC, RF/Analog, noise, and linearity characteristics. This device features a vertically stacked gate oxide structure of HfO2/SiO2 in a dual-source vertical TFET configuration that reflects enhanced ION and better leakage current suppression compared to High-k-dielectric (HfO2)-DS-VTFET. Additionally, in comparison to HfO2-DS-VTFET, the HDG-DS-VTFET showed a reduced threshold voltage ( \({{V}_{{{\text{th}}}}}\) ) of 0.21 V, a lower sub-threshold value of 8.5 mV/decade, and a higher ION/IOFF reflected as 7.1 × 1012. The present work used a calibrated SILVACO technology computer-aided design (TCAD) simulator. The proposed device has been thoroughly examined concerning its RF/Analog performance parameters, such as gate capacitances, gain-bandwidth product (GBP), cut-off frequency ( \({{f}_{t}}\) ), early voltage, intrinsic gain, and compared to a high-k dielectric (HfO2) DS-VTFET structure. Furthermore, a linearity analysis was performed as a figure of merit (FOM), considering several parameters such as the 1-db compression point, the 3rd-order intermodulation intercept point (IIP3), the 3rd-order voltage intercepts point (VIP3), and the 3rd-order intermodulation distortion point (IMD3). In comparison to the high-k dielectric (HfO2) DS-VTFET, the proposed HDG-DS-VTFET showed a significantly reduced sub threshold value of approximately 77% which gives a notably high ON current with low ( \({{V}_{{{\text{th}}}}}\) ) for possible low-power linear and RF applications.
