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Abstract <p>In this manuscript the SRAM cell using 10T is proposed by the use of vertical nanowire tunnel FET. Also, this manuscript compares the present 10T-SRAM cells along with other type of SRAM having different transistor combinations. The topologies are compared for the various performance parameters like leakage power, leakage current, RSNM (Read Signal-to-Noise Margin), WSNM (Write Signal-to-Noise Margin), write delay, read delay etc. Further it is found that the SRAM cell using 10T is producing less leakage power with a correlation of 25–79% over other SRAM cells. RSNM and WSNM are raised by 6–60% and 5–47% respectively over the rest of the topologies for SRAM cell. In this paper we have tried and achieved to reduce leakage power and leakage current with an acceptable write delay, read delay and complexity of the circuit.</p>

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Numerical Comparative Analysis of 10T-SRAM Cells with 6T, 7T, 8T, and 9T Using Vertical Nanowire Tunnel FETs

  • 期刊论文

  • 发表日期：

    2025年5月13日

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  • Amit Das,
  • Anjana Bhardwaj,
  • Ashish Gupta,
  • Geetanjali Raj

摘要

Abstract

In this manuscript the SRAM cell using 10T is proposed by the use of vertical nanowire tunnel FET. Also, this manuscript compares the present 10T-SRAM cells along with other type of SRAM having different transistor combinations. The topologies are compared for the various performance parameters like leakage power, leakage current, RSNM (Read Signal-to-Noise Margin), WSNM (Write Signal-to-Noise Margin), write delay, read delay etc. Further it is found that the SRAM cell using 10T is producing less leakage power with a correlation of 25–79% over other SRAM cells. RSNM and WSNM are raised by 6–60% and 5–47% respectively over the rest of the topologies for SRAM cell. In this paper we have tried and achieved to reduce leakage power and leakage current with an acceptable write delay, read delay and complexity of the circuit.