Abstract <p>In nanoscale Field Effect Transistors (FETs), short channel effects degrade the electrical performance of the devices. These effects can be minimized by modifying the device structures. The multigate structure is one of the methods that make further miniaturization in the semiconductor industry. In this paper, for 5 nm channel length Silicon nanowire FETs, short channel parameters are analyzed for different geometries and channel orientations. The I-V characteristics are simulated using the OMEN nanowire simulation tool across different cross-sectional areas and channel orientations for three different multigate structures namely Triple Gate (TG), Rectangular Gate All Around (GAA), and Cylindrical Gate All Around (GAA) Si Nanowire FET. Among the three structures, the cylindrical GAA Si nanowire FET exhibits superior performance, with a Drain Induced Barrier Lowering (DIBL) of 76.41 mV/V and a Subthreshold Slope (SS) of 69.38 mV/dec at a 3 nm² cross-sectional area. The current on-off ratio (<i>I</i>_on/<i>I</i>_off) for this structure reaches 2.05 × 10⁷, which is significantly higher than the other configurations. These results indicate that the cylindrical GAA nanowire FET effectively suppresses short-channel effects and improves the current on-off ratio, making it a potential option for advanced low-power devices and VLSI circuits.</p>