Abstract <p>The insertion of repeater elements (buffering) in digital circuits is necessary to control interconnect delays, which play a dominant role in the performance of deep submicron VLSI designs. The synthesis and packing of buffering trees are complicated by the lack of free space after the placement of the main logic gates and by the power constraints. Using inverters instead of buffer elements is generally more efficient in terms of area, power consumption, and timing characteristics. However, it is necessary to maintain the parity of inverters in the path to any receiver in the tree to preserve the logic of the circuit’s operation. For this purpose, various heuristic methods are applied, combining the use of inverters and buffers, but the optimality of the resulting solutions has not been sufficiently studied. In this study, an algorithm for optimizing the buffer tree, based on dynamic programming and replacing the maximum possible number of buffers with inverters, is presented. The algorithm has linear time and space complexities and is quite simple to implement. A statistical analysis of the efficiency of the computed optimal solutions in comparison with the results of well-known simple heuristics is performed. It is established that the best results are achieved in the cases in which the final signal receivers are connected only to the leaves of the buffer tree: the proportion of buffers is reduced on average by a factor of 1.7, and with the maximum of a factor of 3, compared to the heuristic solution.</p>