Abstract <p>An embedded gate-gate all around field effect transistor (EG-GAA) design is proposed through this research study. The device having silicon thickness less than 10 nm is implemented to investigate performance metrics for the core radius dimensions of 2.5 and 5 nm. The quantum-corrected drift and diffusion models are used to accurately capture the quantum confinement mechanism, while mobility models are used to assimilate the intricate effects of both vertical and transverse electric fields, as well as mobility arising from surface scattering. The results obtained with a core radius of 2.5 nm show a significantly higher ON/OFF current ratio of <InlineEquation ID="IEq1"> <EquationSource Format="TEX">\(2.57 \times {{10}^{9}}\)</EquationSource>  </InlineEquation> in 2.5 nm core, approximately an order higher in magnitude than that for 5 nm. With increase in the core radius from 2.5 to 5 nm, the research findings show a <InlineEquation ID="IEq2"> <EquationSource Format="TEX">\(32.07\% \)</EquationSource>  </InlineEquation> decrease in the drain induced barrier lowering (DIBL) and <InlineEquation ID="IEq3"> <EquationSource Format="TEX">\(88.8\% \)</EquationSource>  </InlineEquation> improvement in the transconductance (<InlineEquation ID="IEq4"> <EquationSource Format="TEX">\({{g}_{m}})\)</EquationSource>  </InlineEquation>. The thermal reliability (up to 398 K) of the device and its employability in analog and digital domains are validated through its performance metrics such as ON/OFF current ratio, subthreshold slope (SS), drain induced barrier lowering (DIBL), transconductance generation factor (TGF), cutoff frequency (<InlineEquation ID="IEq5"> <EquationSource Format="TEX">\({{f}_{{\text{C}}}})~\)</EquationSource>  </InlineEquation> and gain bandwidth product (GBW). The sensitivity of the device towards gate oxide thickness, gate work function and dielectric material suggest its possible use in biosensing applications. Finally, a comparison between classical and quantum models validating the scaling possibility is reported. Results of the visualization for electron density variation demonstrate the impact on effective oxide thickness and inversion layer formation. The device is also studied for aging effects that leads to a threshold voltage shift due to oxide trapped charges. With the improved gate controllability, this GAA device structure mitigates the impact of trapped charges even at <InlineEquation ID="IEq6"> <EquationSource Format="TEX">\(\sim {{N}_{{it}}} = {{10}^{{12}}}\,\,{\text{c}}{{{\text{m}}}^{{ - 2}}}.~\)</EquationSource>  </InlineEquation> Also, to justify its superiority, a comparative study on the performance parameters of proposed device with similar devices from the existing research literature is also presented.</p>

Performance Analysis of Vertical Embedded Gate-Gate All Around FET with Quantum Confinement Effects

期刊论文
发表日期：

2025年10月1日

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Amit Saini,
Vishal Narula,
Sangeeta Mangesh

摘要

Abstract

An embedded gate-gate all around field effect transistor (EG-GAA) design is proposed through this research study. The device having silicon thickness less than 10 nm is implemented to investigate performance metrics for the core radius dimensions of 2.5 and 5 nm. The quantum-corrected drift and diffusion models are used to accurately capture the quantum confinement mechanism, while mobility models are used to assimilate the intricate effects of both vertical and transverse electric fields, as well as mobility arising from surface scattering. The results obtained with a core radius of 2.5 nm show a significantly higher ON/OFF current ratio of \(2.57 \times {{10}^{9}}\) in 2.5 nm core, approximately an order higher in magnitude than that for 5 nm. With increase in the core radius from 2.5 to 5 nm, the research findings show a \(32.07\% \) decrease in the drain induced barrier lowering (DIBL) and \(88.8\% \) improvement in the transconductance ( \({{g}_{m}})\) . The thermal reliability (up to 398 K) of the device and its employability in analog and digital domains are validated through its performance metrics such as ON/OFF current ratio, subthreshold slope (SS), drain induced barrier lowering (DIBL), transconductance generation factor (TGF), cutoff frequency ( \({{f}_{{\text{C}}}})~\) and gain bandwidth product (GBW). The sensitivity of the device towards gate oxide thickness, gate work function and dielectric material suggest its possible use in biosensing applications. Finally, a comparison between classical and quantum models validating the scaling possibility is reported. Results of the visualization for electron density variation demonstrate the impact on effective oxide thickness and inversion layer formation. The device is also studied for aging effects that leads to a threshold voltage shift due to oxide trapped charges. With the improved gate controllability, this GAA device structure mitigates the impact of trapped charges even at \(\sim {{N}_{{it}}} = {{10}^{{12}}}\,\,{\text{c}}{{{\text{m}}}^{{ - 2}}}.~\) Also, to justify its superiority, a comparative study on the performance parameters of proposed device with similar devices from the existing research literature is also presented.