TCAD Simulation of a Heavy Charged Particle Impact on an n-MOS Structure as a Part of a Memory Cell

When designing radiation-hardened integrated circuits (IC), especially memory chips, it becomes necessary to consider the propagation of currents caused by a heavy charged particle (HCP) entering the device. Scaling of semiconductor processes and higher circuit density increases the probability of multiple cell upset (MCU) caused by diffusion currents. The analysis of these effects is a complex computational problem, the complexity of solving which increases as the physical dimensions of the elements decrease. This paper proposes an approach based on using TCAD capabilities for simulating nanoscale IC structures. A model in cylindrical coordinates for the charge generation and collection after the HCP impact on a MOS structure simulation is presented. The described approach allows us to quickly estimate the values of the diffusion current caused by an HCP passing through a region of a certain area. Applying this technique to a memory cell makes it possible to determine the distance from the charged particle strike point at which the diffusion current exceeds the cell critical current and the failure occurs. This allows us to assess the probability of MCU and adjust the IC’s layout, taking these factors into account, and estimate the error cross-section before manufacturing and testing the chip.