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Abstract <p>This paper presents the design and implementation of a layout of the D flip flop and integrates into a configurable logic block (CLB) using quantum-dot cellular automata (QCA), a promising ultra-fast and low power nanotechnology. QCA, in fact, overcomes the issues of CMOS technology like sub-threshold leakage currents, short channel effects and etc. The CLB is a fundamental building block of the FPGA, enabling users to create custom digital logic circuits to suit specific application requirements. The D flip flop is an essential sequential logic element used to store and synchronize data in digital systems. The proposed D flip flop hasa reset pin which is used to make output to zero irrespective of clock and input conditions. This paper describes the logic design of the D flip flop, including the schematic representation and truth table, showcasing its ability to store data on the rising or falling edge of the clock signal. Furthermore, the D flip flop is integrated into the CLB, taking advantage of multiplexer based 4-input look-up tables (LUTs) and programmable routing resources for signal propagation and control using quantum cells. To validate the functionality of the D flip flop in the CLB, we have conducted extensive simulations using QCADesigner tool. The proposed D&#xa0;flipflop has been implemented with 28 number of quantum cells in a small area of 0.03 µm<sup>2</sup> with a delay of 1 clock cycle. Moreover, the configurable logic block has been built with the help of the proposed D flip flop’s layout and is proven to be the best among existing modules. The CLB architecture employs 640 quantum cells spread across 1.38 µm<sup>2</sup>, 3 clock cycles delay, and a power dissipation of 39.33 nW.</p>

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Design and Analysis of Ultra-Low Power and High-Speed Configurable Logic Block Using a Memory Element for FPGA

  • 期刊论文

  • 发表日期：

    2025年6月1日

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  • Anjaiah Talamala,
  • Dr. Ajit Kumar Patro,
  • Dr. Kishore Pinninti

摘要

Abstract

This paper presents the design and implementation of a layout of the D flip flop and integrates into a configurable logic block (CLB) using quantum-dot cellular automata (QCA), a promising ultra-fast and low power nanotechnology. QCA, in fact, overcomes the issues of CMOS technology like sub-threshold leakage currents, short channel effects and etc. The CLB is a fundamental building block of the FPGA, enabling users to create custom digital logic circuits to suit specific application requirements. The D flip flop is an essential sequential logic element used to store and synchronize data in digital systems. The proposed D flip flop hasa reset pin which is used to make output to zero irrespective of clock and input conditions. This paper describes the logic design of the D flip flop, including the schematic representation and truth table, showcasing its ability to store data on the rising or falling edge of the clock signal. Furthermore, the D flip flop is integrated into the CLB, taking advantage of multiplexer based 4-input look-up tables (LUTs) and programmable routing resources for signal propagation and control using quantum cells. To validate the functionality of the D flip flop in the CLB, we have conducted extensive simulations using QCADesigner tool. The proposed D flipflop has been implemented with 28 number of quantum cells in a small area of 0.03 µm2 with a delay of 1 clock cycle. Moreover, the configurable logic block has been built with the help of the proposed D flip flop’s layout and is proven to be the best among existing modules. The CLB architecture employs 640 quantum cells spread across 1.38 µm2, 3 clock cycles delay, and a power dissipation of 39.33 nW.