Leveraging 7-nm FinFET Technology for 1-Bit Full Adder Design: Comprehensive Analysis for Smart Applications

This research provides a detailed analysis of one-bit full adder circuits implemented using 7 nm FinFET high performance (HP) and low standby power (LSTP) predictive technology models. The goal is to validate the most optimized design approach based on performance metrics. In the latter part of the study, we justify the most optimized adder design identified in the initial analysis by incorporating thermal and flicker noise parameters into the models and using the Verilog-A BSIM-MG device for further validation. This pioneering study conducts an in-depth investigation of the 7 nm technology node for adder analysis. The optimized adder identified shows a 28% improvement in PDP value compared to its reference adder circuit, benefiting from the inherent area advantage of the 7 nm technology and a reduced operating voltage requirement, which is crucial for low power applications.