Scholarlink

Abstract <p>Designing any analog or digital circuit with low power is the main theme of the present digital world. Reversible logic plays an important role in reducing power. Reversible logic is being implemented both in the forward and backward directions. Reversible logic decreases power by eliminating power loss when one bit of information is lost in simple operations. The implementation of more complex circuits with less power dissipation is being designed by reversible logic gates. Nowadays the usage of reversible gates is prominent in designing logic circuits. The circuits may be analog or digital. This logic is fit to Low power CMOS, DNA computing, nanotechnology, and quantum computing. The Half adder, Full adder, Half subtractor, and Full subtractor are combinational circuits whose output depends on the present inputs only. Now, these combinational circuits are implemented by using reversible logic. This manuscript presents implementation of Half adder, Full adder, Half subtractor, and Full subtractor using MEDD gate. The single MEDD gate performs four combinational circuits 4 : 2 encoder, 2 : 4 Decoder, 2–1 Multiplexer, and 1–2 Demultiplexer. The proposed one is suitable for designing the circuits to respond fast and makes use of the less power. The logic of these circuits is verified using Xilinx Vivado 2019.1 version software tool.</p>

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Design of Binary Adders and Subtractors Using MEDD Gate

  • 期刊论文

  • 发表日期：

    2025年2月1日

查看全文
  • S. Sharmila Banu,
  • Syed Zahiruddin

摘要

Abstract

Designing any analog or digital circuit with low power is the main theme of the present digital world. Reversible logic plays an important role in reducing power. Reversible logic is being implemented both in the forward and backward directions. Reversible logic decreases power by eliminating power loss when one bit of information is lost in simple operations. The implementation of more complex circuits with less power dissipation is being designed by reversible logic gates. Nowadays the usage of reversible gates is prominent in designing logic circuits. The circuits may be analog or digital. This logic is fit to Low power CMOS, DNA computing, nanotechnology, and quantum computing. The Half adder, Full adder, Half subtractor, and Full subtractor are combinational circuits whose output depends on the present inputs only. Now, these combinational circuits are implemented by using reversible logic. This manuscript presents implementation of Half adder, Full adder, Half subtractor, and Full subtractor using MEDD gate. The single MEDD gate performs four combinational circuits 4 : 2 encoder, 2 : 4 Decoder, 2–1 Multiplexer, and 1–2 Demultiplexer. The proposed one is suitable for designing the circuits to respond fast and makes use of the less power. The logic of these circuits is verified using Xilinx Vivado 2019.1 version software tool.