Abstract <p>The accrual of interface trap charges (ITC) at the margin of InAs/SiO<sub>2</sub> and HfO<sub>2</sub> interfaces considerably influences the performance and reliability of tunnel field effect transistor (TFET) devices, emphasising the need to address this issue. This work provides a thorough analysis of how interface trap charges (ITCs) affect the suggested device, the nonuniform InAs-channel dual metal hetero-oxide double-gate TFET (InAs-NUC-TFET), in terms of critical performance metrics like DC characteristics and analog/RF electrical performance. Both positive and negative ITCs were analysed to determine how they affected the device. The results demonstrate that variations in ITC concentrations have little impact on the device’s performance metrics, emphasising that InAs-NUC-TFETs are more resilient to ITCs compared to conventional semiconductor devices, which frequently suffer significant performance due to ITCs. For trap charges with minimum values of –1 × 10<sup>12</sup> and maximum values of 1 × 10<sup>12</sup>, the deviations in ON-current, OFF-current, and their ratio are 26, 18, and 10%, respectively. In addition to demonstrating resistance to trap charges, the device has a high current ratio (4.32 × 10<sup>13</sup>) and an ON-current in milli-amperes. It is positioned as a possible contender for future electronics, especially for low power and high frequency applications, due to its remarkable performance under various situations and resistance to ITCs.</p>

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Interface Trap-Induced Impact in Linearity and Small-Signal Performance of InAs-Channel TFETs: Reliability Implications

  • Vedvrat,
  • Rajeev Kumar Sachan

摘要

Abstract

The accrual of interface trap charges (ITC) at the margin of InAs/SiO2 and HfO2 interfaces considerably influences the performance and reliability of tunnel field effect transistor (TFET) devices, emphasising the need to address this issue. This work provides a thorough analysis of how interface trap charges (ITCs) affect the suggested device, the nonuniform InAs-channel dual metal hetero-oxide double-gate TFET (InAs-NUC-TFET), in terms of critical performance metrics like DC characteristics and analog/RF electrical performance. Both positive and negative ITCs were analysed to determine how they affected the device. The results demonstrate that variations in ITC concentrations have little impact on the device’s performance metrics, emphasising that InAs-NUC-TFETs are more resilient to ITCs compared to conventional semiconductor devices, which frequently suffer significant performance due to ITCs. For trap charges with minimum values of –1 × 1012 and maximum values of 1 × 1012, the deviations in ON-current, OFF-current, and their ratio are 26, 18, and 10%, respectively. In addition to demonstrating resistance to trap charges, the device has a high current ratio (4.32 × 1013) and an ON-current in milli-amperes. It is positioned as a possible contender for future electronics, especially for low power and high frequency applications, due to its remarkable performance under various situations and resistance to ITCs.