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<p>As the world increasingly embraces AI across critical domains such as healthcare and national security, conventional CMOS-based architectures struggle to meet the computational demands of Deep Neural Networks. Emerging technologies, such as Spin-Orbit Torque Magnetic Tunnel Junctions (SOT-MTJs), enable In-Memory Analog Computing (IMAC) architectures that offer substantial improvements in power efficiency and performance. However, Process Variation (PV) significantly impacts SOT-MTJ Magnetoresistive Random Access Memory (MRAM) performance by causing resistance shifts that induce bit-flips in memristive crossbar arrays, which results in degraded inference accuracy and reliability. In this work, we investigate the architectural-level impact of PV on inference accuracy and introduce a post-training weight mapping approach to mitigate faults in SOT-MRAM devices. We propose a Variation Impact Score (VIS) metric to quantify sub-array fault sensitivity and a Fault Observation Window (FOW) framework to localize vulnerable crossbar regions. Building on this analysis, we develop a VIS-guided dynamic weight-mapping module integrated with the IMAC-Sim presilicon framework that relocates critical weights from high-VIS FOWs to reliable regions without model retraining. Using SPICE-level evaluations, we demonstrate consistent accuracy recovery under severe process-induced faults, with recovery in early layers and substantial gains in the final decision layer, ensuring robust and reliable IMAC architectures despite hardware-induced bit-flips.</p>

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Dyn-A-Map: Dynamic AI-Model Mapping for robust and accurate MRAM-based analog edge computing

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年6月15日

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  • Muhtasim Alam Chowdhury,
  • Ramtin Zand,
  • Soheil Salehi

摘要

As the world increasingly embraces AI across critical domains such as healthcare and national security, conventional CMOS-based architectures struggle to meet the computational demands of Deep Neural Networks. Emerging technologies, such as Spin-Orbit Torque Magnetic Tunnel Junctions (SOT-MTJs), enable In-Memory Analog Computing (IMAC) architectures that offer substantial improvements in power efficiency and performance. However, Process Variation (PV) significantly impacts SOT-MTJ Magnetoresistive Random Access Memory (MRAM) performance by causing resistance shifts that induce bit-flips in memristive crossbar arrays, which results in degraded inference accuracy and reliability. In this work, we investigate the architectural-level impact of PV on inference accuracy and introduce a post-training weight mapping approach to mitigate faults in SOT-MRAM devices. We propose a Variation Impact Score (VIS) metric to quantify sub-array fault sensitivity and a Fault Observation Window (FOW) framework to localize vulnerable crossbar regions. Building on this analysis, we develop a VIS-guided dynamic weight-mapping module integrated with the IMAC-Sim presilicon framework that relocates critical weights from high-VIS FOWs to reliable regions without model retraining. Using SPICE-level evaluations, we demonstrate consistent accuracy recovery under severe process-induced faults, with recovery in early layers and substantial gains in the final decision layer, ensuring robust and reliable IMAC architectures despite hardware-induced bit-flips.