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<p>Emerging processing-in-memory (PIM) architectures using memristors and analog computing face reliability issues from device non-idealities and noise. While error-correcting codes (ECCs) are vital, existing methods suffer from discontinuity and inefficiency. We propose a non-binary low-density parity-check (NB-LDPC) code over Galois field (GF) to address this. The design employs a 1024-symbol information word with 64 GF(3)-encoded check symbols, achieving 8-symbol error correction and compatibility with multi-level memory cells. A 40 nm prototype chip demonstrates: 59.65 ×lower bit error rate, 1.562 ×better power efficiency, and seamless operation without dataflow interruption. This GF-based approach enables unified error correction for memory and computation, resolving key reliability-performance trade-offs in neuro-inspired hardware, paving the way for robust PIM systems.</p>

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Correcting processing-in-memory multiply-accumulate arithmetic errors with LDPC

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2026年3月18日

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  • Daijing Shi,
  • Yihan Fu,
  • Yihang Zhu,
  • Anjunyi Fan,
  • Yaoyu Tao,
  • Bonan Yan,
  • Yuchao Yang

摘要

Emerging processing-in-memory (PIM) architectures using memristors and analog computing face reliability issues from device non-idealities and noise. While error-correcting codes (ECCs) are vital, existing methods suffer from discontinuity and inefficiency. We propose a non-binary low-density parity-check (NB-LDPC) code over Galois field (GF) to address this. The design employs a 1024-symbol information word with 64 GF(3)-encoded check symbols, achieving 8-symbol error correction and compatibility with multi-level memory cells. A 40 nm prototype chip demonstrates: 59.65 ×lower bit error rate, 1.562 ×better power efficiency, and seamless operation without dataflow interruption. This GF-based approach enables unified error correction for memory and computation, resolving key reliability-performance trade-offs in neuro-inspired hardware, paving the way for robust PIM systems.