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<p>We present a low-power analog CMOS reservoir computing chip that employs a simple ring topology for unidirectional nonlinear analog processing. Each node integrates a sample-and-hold circuit operating at 1 kHz, enabling compact and energy-efficient implementation in standard CMOS. The fabricated chip was evaluated on standard benchmarks, achieving a linear memory capacity of 13.4 and information processing capacities of 7.2 (second-order), 3.3 (third-order), and 1.2 (fourth-order). It also demonstrated competitive accuracy in both short- and long-term time-series forecasting tasks. Most notably, this performance was achieved with a power dissipation of only 20 <i>μ</i>W per core, highlighting the potential of analog CMOS reservoir computing for deployment in energy-constrained edge devices.</p>

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Demonstration of a subthreshold analog CMOS reservoir chip for temporal signal processing

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年3月2日

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  • Shimon Matsuno,
  • Abe Yuki,
  • Kota Ando,
  • Kazuki Nakada,
  • Eiji Suzuki,
  • Keita Suda,
  • Yukihiro Urakawa,
  • Shin-ichiro Mochizuki,
  • Yukio Terasaki,
  • Tomoyuki Sasaki,
  • Tetsuya Asai

摘要

We present a low-power analog CMOS reservoir computing chip that employs a simple ring topology for unidirectional nonlinear analog processing. Each node integrates a sample-and-hold circuit operating at 1 kHz, enabling compact and energy-efficient implementation in standard CMOS. The fabricated chip was evaluated on standard benchmarks, achieving a linear memory capacity of 13.4 and information processing capacities of 7.2 (second-order), 3.3 (third-order), and 1.2 (fourth-order). It also demonstrated competitive accuracy in both short- and long-term time-series forecasting tasks. Most notably, this performance was achieved with a power dissipation of only 20 μW per core, highlighting the potential of analog CMOS reservoir computing for deployment in energy-constrained edge devices.