<p>Neuromorphic computing takes biological inspiration to the device level aiming to improve computational efficiency and capabilities. One of the major issues that arises is the training of neuromorphic hardware systems. Typically training algorithms require global information and are thus inefficient to implement directly in hardware. In this paper we describe a set of reinforcement learning based, local weight update rules and their implementation in superconducting hardware. Using SPICE circuit simulations, we implement a small-scale neural network with a learning time of order one nanosecond per update. This network can be trained to learn new functions simply by changing the target output for a given set of inputs, without the need for any external adjustments to the network. Further, this architecture does not require programing explicit weight values in the network, alleviating a critical challenge with analog hardware implementations of neural networks.</p>

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A self-training spiking superconducting neuromorphic architecture

  • M. L. Schneider,
  • E. M. Jué,
  • M. R. Pufall,
  • K. Segall,
  • C. W. Anderson

摘要

Neuromorphic computing takes biological inspiration to the device level aiming to improve computational efficiency and capabilities. One of the major issues that arises is the training of neuromorphic hardware systems. Typically training algorithms require global information and are thus inefficient to implement directly in hardware. In this paper we describe a set of reinforcement learning based, local weight update rules and their implementation in superconducting hardware. Using SPICE circuit simulations, we implement a small-scale neural network with a learning time of order one nanosecond per update. This network can be trained to learn new functions simply by changing the target output for a given set of inputs, without the need for any external adjustments to the network. Further, this architecture does not require programing explicit weight values in the network, alleviating a critical challenge with analog hardware implementations of neural networks.