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<p>Solving optimization problems is a highly demanding workload requiring high-performance computing systems. Optimization solvers are usually difficult to parallelize in conventional digital architectures, particularly when stochastic decisions are involved. Recently, analog computing architectures for accelerating stochastic optimization solvers have been presented, but they were limited to academic problems in quadratic polynomial format. Here we present KLIMA, a <i>k</i> − <b>L</b>ocal <b>I</b>n-<b>M</b>emory <b>A</b>ccelerator with resistive Content Addressable Memories (CAMs) and Dot-Product Engines (DPEs) to accelerate the solution of high-order industry-relevant optimization problems, in particular Boolean Satisfiability. By co-designing the optimization heuristics and circuit architecture we improve the speed and energy to the solution up to 182 × compared to the digital state of the art.</p>

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Solving Boolean satisfiability problems with resistive content addressable memories

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2025年4月2日

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  • Giacomo Pedretti,
  • Fabian Böhm,
  • Tinish Bhattacharya,
  • Arne Heittmann,
  • Xiangyi Zhang,
  • Mohammad Hizzani,
  • George Hutchinson,
  • Dongseok Kwon,
  • John Moon,
  • Elisabetta Valiante,
  • Ignacio Rozada,
  • Catherine E. Graves,
  • Jim Ignowski,
  • Masoud Mohseni,
  • John Paul Strachan,
  • Dmitri Strukov,
  • Ray Beausoleil,
  • Thomas Van Vaerenbergh

摘要

Solving optimization problems is a highly demanding workload requiring high-performance computing systems. Optimization solvers are usually difficult to parallelize in conventional digital architectures, particularly when stochastic decisions are involved. Recently, analog computing architectures for accelerating stochastic optimization solvers have been presented, but they were limited to academic problems in quadratic polynomial format. Here we present KLIMA, a k − Local In-Memory Accelerator with resistive Content Addressable Memories (CAMs) and Dot-Product Engines (DPEs) to accelerate the solution of high-order industry-relevant optimization problems, in particular Boolean Satisfiability. By co-designing the optimization heuristics and circuit architecture we improve the speed and energy to the solution up to 182 × compared to the digital state of the art.