<p>In this work, we propose a novel differential photonic static random access memory (pSRAM) bitcell design using fabrication-friendly photonic components. The proposed pSRAM overcomes the key limitations of traditional electrical SRAMs, which struggle with speed and power efficiency due to increasing bitline/wordline capacitance and interconnect resistance associated with long electrical wires as technology scales. By utilizing cross-coupled micro-ring resonators and differential photodiode structures, along with optical waveguides instead of traditional wordlines and bitlines, our pSRAM exhibits high-speed, and energy-efficient performance. The pSRAM bitcell demonstrates a read/write speed of 40 GHz, with a switching (static) energy consumption of approximately 0.6 pJ (0.03 pJ) per bit and a footprint of 330 × 290 <i>μ</i><i>m</i><sup>2</sup> using the GlobalFoundries 45SPCLO process node. These bitcells can be arranged into a 2D memory array, enabling large-scale, on-chip photonic memory subsystems ideal for high-speed memory, data processing and computing applications.</p>

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Design of Energy-Efficient Cross-coupled Differential Photonic-SRAM (pSRAM) Bitcell for High-Speed On-Chip Photonic Memory and Compute Systems

  • Md Abdullah-Al Kaiser,
  • Sugeet Sunder,
  • Clynn Mathew,
  • Michal Rakowski,
  • Ajey P. Jacob,
  • Akhilesh R. Jaiswal

摘要

In this work, we propose a novel differential photonic static random access memory (pSRAM) bitcell design using fabrication-friendly photonic components. The proposed pSRAM overcomes the key limitations of traditional electrical SRAMs, which struggle with speed and power efficiency due to increasing bitline/wordline capacitance and interconnect resistance associated with long electrical wires as technology scales. By utilizing cross-coupled micro-ring resonators and differential photodiode structures, along with optical waveguides instead of traditional wordlines and bitlines, our pSRAM exhibits high-speed, and energy-efficient performance. The pSRAM bitcell demonstrates a read/write speed of 40 GHz, with a switching (static) energy consumption of approximately 0.6 pJ (0.03 pJ) per bit and a footprint of 330 × 290 μm2 using the GlobalFoundries 45SPCLO process node. These bitcells can be arranged into a 2D memory array, enabling large-scale, on-chip photonic memory subsystems ideal for high-speed memory, data processing and computing applications.