<p>As Moore’s law approaches its limits, chalcogenides offer a promising route to next-generation computing and sensing, thanks to their topological, magnetoelectric, excitonic, and spintronic properties. Yet the same traits that make them appealing, e.g., exotic properties at monolayer thickness, clean van der Waals interfaces, and strong many-body effects, also heighten sensitivity to fabrication, hindering translation into scalable devices. Progress is further constrained by fragmented knowledge across synthesis, processing, and integration, and by the lack of systematic links between fabrication parameters and performance metrics. This Perspective examines key obstacles in controlling chalcogenide heterostructures and stresses the need for an integrated co-design framework, uniting materials growth, processing, and device architecture to accelerate practical technologies.</p>

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Next-generation electronics by co-design with chalcogenide materials

  • Debarghya Mallick,
  • Sujoy Ghosh,
  • An-Hsi Chen,
  • Jian Liao,
  • Jinkyoung Yoo,
  • Qiangsheng Lu,
  • Steven J. Randolph,
  • Scott T. Retterer,
  • Gyula Eres,
  • Yong P. Chen,
  • Leonid P. Rokhinson,
  • Matthew Brahlek,
  • Robert G. Moore

摘要

As Moore’s law approaches its limits, chalcogenides offer a promising route to next-generation computing and sensing, thanks to their topological, magnetoelectric, excitonic, and spintronic properties. Yet the same traits that make them appealing, e.g., exotic properties at monolayer thickness, clean van der Waals interfaces, and strong many-body effects, also heighten sensitivity to fabrication, hindering translation into scalable devices. Progress is further constrained by fragmented knowledge across synthesis, processing, and integration, and by the lack of systematic links between fabrication parameters and performance metrics. This Perspective examines key obstacles in controlling chalcogenide heterostructures and stresses the need for an integrated co-design framework, uniting materials growth, processing, and device architecture to accelerate practical technologies.