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<p>Monolithic three-dimensional (3D) integration—collocating logic and memory in the back-end-of-line (BEOL)—offers higher bandwidth, lower latency, and improved energy efficiency for AI, cloud, and edge systems. Pairing two-dimensional <i>p</i>-type semiconductors with oxide n-channel transistors establishes a practical basis for complementary BEOL CMOS. This Review assesses manufacturing-aligned pathways to high-performance 2D p-channel transistors, covering transfer-free low-temperature growth, clean van der Waals contacts, gentle p-doping, and mitigation of crystallization, volatility, and interdiffusion. Recent gain-cell and vertical complementary field-effect transistor (CFET) demonstrations are examined, and a pragmatic outlook for BEOL p-type 2D semiconductors is outlined toward manufacturable, dense, low-power monolithic 3D chips.</p>

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Bridging the p-type gap in oxide electronics with 2D semiconductors

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年7月7日

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  • Taikyu Kim,
  • Seokhyun Hwang,
  • Jae Kyeong Jeong

摘要

Monolithic three-dimensional (3D) integration—collocating logic and memory in the back-end-of-line (BEOL)—offers higher bandwidth, lower latency, and improved energy efficiency for AI, cloud, and edge systems. Pairing two-dimensional p-type semiconductors with oxide n-channel transistors establishes a practical basis for complementary BEOL CMOS. This Review assesses manufacturing-aligned pathways to high-performance 2D p-channel transistors, covering transfer-free low-temperature growth, clean van der Waals contacts, gentle p-doping, and mitigation of crystallization, volatility, and interdiffusion. Recent gain-cell and vertical complementary field-effect transistor (CFET) demonstrations are examined, and a pragmatic outlook for BEOL p-type 2D semiconductors is outlined toward manufacturable, dense, low-power monolithic 3D chips.