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<p>Quantum random number generators allow for access of a truly unpredictable random sequence. A popular scheme is based on the laser phase noise, which, however, is generally limited in speed and implementation complexity, especially for chip integration. In this work, a general physical model based on the Wiener process for such schemes is introduced, through which the limitation on generation speed is clearly explained and comprehensive optimization is achieved. We present an insight to exploit the potential frequency band of a quantum entropy source with a simple filtering method and experimentally boost the bandwidth to 20 GHz, where an ultra-fast generation rate of 156 Gbps is demonstrated. Our proposal significantly enhances the ceiling speed of such schemes without requiring extra complex hardware, thus effectively benefiting the corresponding chip integration with high performance and low implementation cost, paving the way for its large-scale applications.</p>

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An ultra-fast quantum random number generation scheme based on laser phase noise

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2025年12月5日

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  • Jie Yang,
  • Mei Wu,
  • Yichen Zhang,
  • Yang Li,
  • Wei Huang,
  • Heng Wang,
  • Yan Pan,
  • Qi Su,
  • Yiming Bian,
  • Haoyuan Jiang,
  • Song Yu,
  • Bingjie Xu,
  • Bin Luo,
  • Hong Guo

摘要

Quantum random number generators allow for access of a truly unpredictable random sequence. A popular scheme is based on the laser phase noise, which, however, is generally limited in speed and implementation complexity, especially for chip integration. In this work, a general physical model based on the Wiener process for such schemes is introduced, through which the limitation on generation speed is clearly explained and comprehensive optimization is achieved. We present an insight to exploit the potential frequency band of a quantum entropy source with a simple filtering method and experimentally boost the bandwidth to 20 GHz, where an ultra-fast generation rate of 156 Gbps is demonstrated. Our proposal significantly enhances the ceiling speed of such schemes without requiring extra complex hardware, thus effectively benefiting the corresponding chip integration with high performance and low implementation cost, paving the way for its large-scale applications.