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<p>The sustainable development of artificial intelligence requires energy-efficient computing technology. Two-dimensional semiconductor digital electronics could potentially provide such capabilities, and promising single devices and small circuits have been developed. However, very large-scale integration remains challenging due to the inability to control atomic-scale defects and mesoscopic device variations, as well as the lack of macroscopic variation-aware design methodology. Here we report a molybdenum disulfide computer that combines a 0.5-μm industrial fabrication process and a back-end-of-line-integrated academia laboratory process. The computer comprises 1,433 transistors interconnected by four metal layers within a compact footprint, offering an integration density of around 9,336 transistors per square millimetre. The computer can store data on-chip in the register file and perform arithmetic operations on multiple-bit data parallelly at a 1-kHz clock frequency. Key to the development of this system is a multi-level co-optimization methodology that spans transistor, standard cell, logic synthesis and interconnect design.</p>

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A bit-parallel molybdenum disulfide computer built through multi-level co-optimization

  • 期刊论文

  • 发表日期：

    2026年5月26日

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  • Dongxu Fan,
  • Yun Mao,
  • Hao Qiu,
  • Rui Li,
  • Fei Lu,
  • Wenqiang Yuan,
  • Yibiao Yin,
  • Zhihui Zheng,
  • Zhoushuo Han,
  • Yuan Tian,
  • Xiushan Yan,
  • Taotao Li,
  • Shitong Zhu,
  • Yanbin Li,
  • Weisheng Li,
  • Xuecou Tu,
  • Chunsong Zhao,
  • Jian-Bin Xu,
  • Jeffrey Xu,
  • Yi Shi,
  • Xinran Wang

摘要

The sustainable development of artificial intelligence requires energy-efficient computing technology. Two-dimensional semiconductor digital electronics could potentially provide such capabilities, and promising single devices and small circuits have been developed. However, very large-scale integration remains challenging due to the inability to control atomic-scale defects and mesoscopic device variations, as well as the lack of macroscopic variation-aware design methodology. Here we report a molybdenum disulfide computer that combines a 0.5-μm industrial fabrication process and a back-end-of-line-integrated academia laboratory process. The computer comprises 1,433 transistors interconnected by four metal layers within a compact footprint, offering an integration density of around 9,336 transistors per square millimetre. The computer can store data on-chip in the register file and perform arithmetic operations on multiple-bit data parallelly at a 1-kHz clock frequency. Key to the development of this system is a multi-level co-optimization methodology that spans transistor, standard cell, logic synthesis and interconnect design.