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<p>Two-dimensional (2D) semiconductors have the potential to replace silicon in next-generation electronic devices. However, despite advances in proof-of-concept device demonstrations and wafer-scale crystal synthesis, the lack of a compatible residue-free patterning technology has hindered industrialization. Here we describe a metal-stamp imprinting method for patterning 2D films into high-quality wafer-scale arrays without introducing chemical or polymer residues. A metal stamp with a three-dimensional morphology is used to form a local contact at the stamp–2D interface. The process selectively exfoliates some of the 2D material while leaving 2D arrays on the growth substrate. Microscopy and spectroscopy characterizations confirmed the clean surface and undamaged crystal structure. A statistical analysis of 100 back-gated molybdenum disulfide (MoS<sub>2</sub>) transistors and 500 top-gated logic circuits found a 20-times-lower variation of the threshold voltage compared to a reactive-ion-etching-based patterning process. The device yield on a 2-inch wafer was 97.6%.</p>

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Residue-free wafer-scale direct imprinting of two-dimensional materials

  • 期刊论文

  • 发表日期：

    2025年7月1日

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  • Zhiwei Li,
  • Xiao Liu,
  • Jiayu Shi,
  • Xiangbin Cai,
  • Yan Zhang,
  • Wenduo Chen,
  • Yuhao Jin,
  • Hao Jiang,
  • So Yeon Kim,
  • Chao Zhu,
  • Ya Deng,
  • Yanran Liu,
  • X. Renshaw Wang,
  • Taotao Li,
  • Ju Li,
  • Zheng Liu,
  • Hongbing Cai,
  • Weibo Gao

摘要

Two-dimensional (2D) semiconductors have the potential to replace silicon in next-generation electronic devices. However, despite advances in proof-of-concept device demonstrations and wafer-scale crystal synthesis, the lack of a compatible residue-free patterning technology has hindered industrialization. Here we describe a metal-stamp imprinting method for patterning 2D films into high-quality wafer-scale arrays without introducing chemical or polymer residues. A metal stamp with a three-dimensional morphology is used to form a local contact at the stamp–2D interface. The process selectively exfoliates some of the 2D material while leaving 2D arrays on the growth substrate. Microscopy and spectroscopy characterizations confirmed the clean surface and undamaged crystal structure. A statistical analysis of 100 back-gated molybdenum disulfide (MoS2) transistors and 500 top-gated logic circuits found a 20-times-lower variation of the threshold voltage compared to a reactive-ion-etching-based patterning process. The device yield on a 2-inch wafer was 97.6%.