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<p>Federated learning provides a framework for multiple participants to collectively train a neural network while maintaining data privacy, and is commonly achieved through homomorphic encryption. However, implementation of this approach at a local edge requires key generation, error polynomial generation and extensive computation, resulting in substantial time and energy consumption. Here, we report a memristor compute-in-memory chip architecture with an in situ physical unclonable function for key generation and an in situ true random number generator for error polynomial generation. Our architecture—which includes a competing-forming array operation method, a compute-in-memory based entropy extraction circuit design and a redundant residue number system-based encoding scheme—allows low error-rate computation, the physical unclonable function and the true random number generator to be implemented within the same memristor array and peripheral circuits. To illustrate the functionality of this memristor-based federated learning, we conduct a case study in which four participants cotrain a two-layered long short-term memory network with 482 weights for sepsis prediction. The test accuracy on the 128-kb memristor array is only 0.12% lower than that achieved with software centralized learning. Our approach also exhibits reduced energy and time consumption compared with conventional digital federated learning.</p>

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Federated learning using a memristor compute-in-memory chip with in situ physical unclonable function and true random number generator

  • 期刊论文

  • 发表日期：

    2025年5月29日

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  • Xueqi Li,
  • Bin Gao,
  • Qi Qin,
  • Peng Yao,
  • Jiaming Li,
  • Han Zhao,
  • Chenji Liu,
  • Qingtian Zhang,
  • Zhenqi Hao,
  • Yang Li,
  • Dequn Kong,
  • Jikang Xu,
  • Jie Yang,
  • Jianshi Tang,
  • Yawen Niu,
  • Xiaobing Yan,
  • He Qian,
  • Huaqiang Wu

摘要

Federated learning provides a framework for multiple participants to collectively train a neural network while maintaining data privacy, and is commonly achieved through homomorphic encryption. However, implementation of this approach at a local edge requires key generation, error polynomial generation and extensive computation, resulting in substantial time and energy consumption. Here, we report a memristor compute-in-memory chip architecture with an in situ physical unclonable function for key generation and an in situ true random number generator for error polynomial generation. Our architecture—which includes a competing-forming array operation method, a compute-in-memory based entropy extraction circuit design and a redundant residue number system-based encoding scheme—allows low error-rate computation, the physical unclonable function and the true random number generator to be implemented within the same memristor array and peripheral circuits. To illustrate the functionality of this memristor-based federated learning, we conduct a case study in which four participants cotrain a two-layered long short-term memory network with 482 weights for sepsis prediction. The test accuracy on the 128-kb memristor array is only 0.12% lower than that achieved with software centralized learning. Our approach also exhibits reduced energy and time consumption compared with conventional digital federated learning.