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<p>Transistors have been shrinking in size and logic cells are getting denser in line with Moore’s law. With aggressive FET scaling and increased chip complexity, thermal management becomes a serious issue in the manufacturing of DVCs. However, the channel length of FETs continues to scale down as CMOS technology advances. Additionally, a more advanced CMOS process causes the supply voltage (V<sub>DD</sub>) decrease steadily, which lowers the output signal swing and gain of the pre-amplifiers in DVCs. FinFET process offers several benefits over traditional bulk MOSFETs at deep nanoscale dimensions. Therefore, in this work, a triple-tail CMOS DVC (TT-DVC-CO) circuit featuring capacitive over-neutralization and two stages of pre-amplifiers is designed and simulated (HSPICE tool) using 7&#xa0;nm FinFET process with a wider V<sub>DD</sub> levels under various operating thermal conditions (T). The 7&#xa0;nm FinFET based TT-DVC-CO circuit exhibits thermal inversion behavior, wherein the circuit exhibits superior speed characteristics with rising temperature over the investigated operating range. This observation is fundamentally different from that of the traditional bulk CMOS DVC circuits, that is, the propagation delay of 7&#xa0;nm FinFET based TT-DVC-CO circuit drops with rising temperature even in the super-threshold regime. The behaviour of TT-DVC-CO circuit with variation in ΔV<sub>IN</sub> under different V<sub>DD</sub> levels and T are also studied using Synopsys HSPICE simulator. This TT-DVC-CO FinFET comparator is highly suitable for future SAR ADCs as well as cryogenic CMOS applications.</p>

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Thermal sensitivity and supply scaling effects on 7 nm FinFET based triple tail dynamic CMOS comparator for automotive/aerospace/electronics industrial applications

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2026年7月11日

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  • Sharvani Yedulapuram,
  • J. Ajayan,
  • Asisa Kumar Panigrahy,
  • L. M. I. Leo Joseph,
  • Deepak Kumar Panda

摘要

Transistors have been shrinking in size and logic cells are getting denser in line with Moore’s law. With aggressive FET scaling and increased chip complexity, thermal management becomes a serious issue in the manufacturing of DVCs. However, the channel length of FETs continues to scale down as CMOS technology advances. Additionally, a more advanced CMOS process causes the supply voltage (VDD) decrease steadily, which lowers the output signal swing and gain of the pre-amplifiers in DVCs. FinFET process offers several benefits over traditional bulk MOSFETs at deep nanoscale dimensions. Therefore, in this work, a triple-tail CMOS DVC (TT-DVC-CO) circuit featuring capacitive over-neutralization and two stages of pre-amplifiers is designed and simulated (HSPICE tool) using 7 nm FinFET process with a wider VDD levels under various operating thermal conditions (T). The 7 nm FinFET based TT-DVC-CO circuit exhibits thermal inversion behavior, wherein the circuit exhibits superior speed characteristics with rising temperature over the investigated operating range. This observation is fundamentally different from that of the traditional bulk CMOS DVC circuits, that is, the propagation delay of 7 nm FinFET based TT-DVC-CO circuit drops with rising temperature even in the super-threshold regime. The behaviour of TT-DVC-CO circuit with variation in ΔVIN under different VDD levels and T are also studied using Synopsys HSPICE simulator. This TT-DVC-CO FinFET comparator is highly suitable for future SAR ADCs as well as cryogenic CMOS applications.