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<p>Many existing Floating-Point (FP) multiplier designs often tend to have high hardware overhead due to additional blocks like lookup tables, correction tables, iterative control structures, or even an unoptimized array of adders. These blocks increase the silicon area, Power Delay Product (PDP), and design complexity. Furthermore, current designs also tend to over-optimize either accuracy or power and performance, but rarely achieve balance across all three metrics. To address this gap, we propose three feed-forward logarithmic FP multipliers -Accurate Logarithmic Floating Point Multiplier (ALFPM), Balanced Logarithmic Floating Point Multiplier (BLFPM), and Compact Logarithmic Floating Point Multiplier (CLFPM). These architectures approximate the logarithms of operands mantissas, sum the logs, and later reconstruct the product via antilogarithm. Log and Antilog approximations employ piece-wise linear approximation, offering a good trade-off between accuracy and hardware efficiency. All designs were implemented in Register Transfer Level (RTL) and evaluated post-layout on the SkyWater 130 nm Process Design Kit (PDK) using the OpenROAD flow. These designs were tested for FP8, BF16, FP16, and FP32 formats. Across precisions, CLFPM achieves the lowest power–delay product (PDP), improving energy efficiency by 10–19%over the existing state-of-the-art architectures, while BLFPM provides the smaller area (5% smaller than SOTA) with up to 23.4% lower PDP. ALFPM delivers the highest numerical accuracy, with Mean Absolute Relative Error Distance (MARED) as low as 2% and minimal bias. Application-level evaluations demonstrate improved JPEG quality compared to the best SOTA, with Peak Signal-to-Noise Ratio increasing by 0.5–4.7 dB. Separately, neural network performance achieves accuracy comparable to exact and leading SOTA across multiple datasets. The proposed multiplier family provides scalable, energy-efficient FP computation suitable for edge computing, Digital Signal Processing, and Artificial Intelligence accelerators.</p>

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Energy-efficient logarithmic floating-point multipliers for neural network and image processing applications

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年7月7日

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  • Anwesh Rao,
  • Gurucharan B S,
  • Tushar M,
  • Shreyas M Iliger,
  • Shylashree N

摘要

Many existing Floating-Point (FP) multiplier designs often tend to have high hardware overhead due to additional blocks like lookup tables, correction tables, iterative control structures, or even an unoptimized array of adders. These blocks increase the silicon area, Power Delay Product (PDP), and design complexity. Furthermore, current designs also tend to over-optimize either accuracy or power and performance, but rarely achieve balance across all three metrics. To address this gap, we propose three feed-forward logarithmic FP multipliers -Accurate Logarithmic Floating Point Multiplier (ALFPM), Balanced Logarithmic Floating Point Multiplier (BLFPM), and Compact Logarithmic Floating Point Multiplier (CLFPM). These architectures approximate the logarithms of operands mantissas, sum the logs, and later reconstruct the product via antilogarithm. Log and Antilog approximations employ piece-wise linear approximation, offering a good trade-off between accuracy and hardware efficiency. All designs were implemented in Register Transfer Level (RTL) and evaluated post-layout on the SkyWater 130 nm Process Design Kit (PDK) using the OpenROAD flow. These designs were tested for FP8, BF16, FP16, and FP32 formats. Across precisions, CLFPM achieves the lowest power–delay product (PDP), improving energy efficiency by 10–19%over the existing state-of-the-art architectures, while BLFPM provides the smaller area (5% smaller than SOTA) with up to 23.4% lower PDP. ALFPM delivers the highest numerical accuracy, with Mean Absolute Relative Error Distance (MARED) as low as 2% and minimal bias. Application-level evaluations demonstrate improved JPEG quality compared to the best SOTA, with Peak Signal-to-Noise Ratio increasing by 0.5–4.7 dB. Separately, neural network performance achieves accuracy comparable to exact and leading SOTA across multiple datasets. The proposed multiplier family provides scalable, energy-efficient FP computation suitable for edge computing, Digital Signal Processing, and Artificial Intelligence accelerators.