<p>Complementary (C) FETs enable superior scaling and electrostatics for sub-3&#xa0;nm nodes but the increased Si/dielectric interface reliability a critical concern, and its impact on Tree-shaped CFETs is investigated for the first time in this work. The Si/dielectric interface trap density (N_it) is varied from 1 to 9 × 10¹² cm^− 2 for both acceptor and donor traps to evaluate their influence on digital, analog, RF, and circuit characteristics. With increasing N_it, in the n-type (p-type) device, acceptor (donor) traps repel electrons (holes), reducing I_ON while suppressing I_OFF by ~ 5 orders, improving the I_ON/I_OFF ratio. In p-type (n-type) device acceptor (donor) traps attract holes (electrons), increasing I_ON by ~ 68% (~ 58%) but reducing the ratio to 10² due to higher leakages. Notably, when the N_it exceeds 4 × 10¹² cm^− 2, the switching ratio deteriorates below 10⁴ for donor (acceptor) traps in the n-type (p-type) device due to pronounced trap-assisted leakage. The findings demonstrate that the Tree-shaped CFET maintains strong electrostatic integrity till ≤ 4 × 10¹² cm^− 2 and stable analog/RF behavior even under severe Si/dielectric interface trap perturbations. The Tree-CFET CMOS inverter shows robust circuit behavior with ~ 2.9 ps delay at moderate trap densities, highlighting the need for precise interface engineering for sub-3&#xa0;nm nodes.</p>