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<p>The I2C (Inter-Integrated Circuit) protocol is a widely adopted two-wire serial communication. Interface controllers are becoming increasingly important in the embedded and Internet of Things (IoT) domains as power savings and tiny communication technologies improve. The work presented here develops and implements an optimised I2C bus controller that significantly reduces power and silicon area without impacting functionality. The controller was designed in Verilog HDL and synthesised with the Open Lane ASIC design pipeline and the Sky130 PDK. It includes enhanced methods such as highly precise clock gating and optimised finite state machines. The recommended controller is successfully created and implemented in Verilog using the OpenLane RTL-to-GDSII flow and the Sky130 CMOS technology library. These support high-speed I2C modes and enable autonomous master-slave communication with minor CPU involvement. Compared to traditional designs, the suggested approach reduces synthesis power by 40.55% and area by 9.8%. Functional accuracy and timeliness were demonstrated using Model Sim and Vivado, while backend verification was secured using DRC, LVS, and XOR checks. This study presents a reliable, silicon-compatible I2C controller designed for integration in high-density and energy-constrained VLSI devices.</p>

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Low-power design and implementation of an enhanced I2C bus controller using open lane: from RTL to GDSII

  • 期刊论文

  • 出版模式：

    开放获取

  • 发表日期：

    2026年5月16日

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  • Gavaskar K,
  • Arun S,
  • Anbumani V,
  • Sathya Narayanan Velmurugan,
  • Mathankumar M

摘要

The I2C (Inter-Integrated Circuit) protocol is a widely adopted two-wire serial communication. Interface controllers are becoming increasingly important in the embedded and Internet of Things (IoT) domains as power savings and tiny communication technologies improve. The work presented here develops and implements an optimised I2C bus controller that significantly reduces power and silicon area without impacting functionality. The controller was designed in Verilog HDL and synthesised with the Open Lane ASIC design pipeline and the Sky130 PDK. It includes enhanced methods such as highly precise clock gating and optimised finite state machines. The recommended controller is successfully created and implemented in Verilog using the OpenLane RTL-to-GDSII flow and the Sky130 CMOS technology library. These support high-speed I2C modes and enable autonomous master-slave communication with minor CPU involvement. Compared to traditional designs, the suggested approach reduces synthesis power by 40.55% and area by 9.8%. Functional accuracy and timeliness were demonstrated using Model Sim and Vivado, while backend verification was secured using DRC, LVS, and XOR checks. This study presents a reliable, silicon-compatible I2C controller designed for integration in high-density and energy-constrained VLSI devices.