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<p>Static random-access memory (SRAM) design at nanoscale dimensions faces critical challenges arising from degraded stability, excessive power dissipation, and heightened sensitivity to process variations, particularly under low-voltage operation. To address these limitations, this paper proposes a robust and energy-efficient carbon nanotube field-effect transistor (CNTFET)-based nine-transistor (9T) SRAM cell architecture optimized for low-power applications. The proposed design employs a fully decoupled read and write structure with a single-ended access scheme, effectively eliminating read-disturb and half-select failures while enhancing overall noise immunity. Read stability is significantly improved by isolating the storage nodes from the read bitline, enabling the read static noise margin (RSNM) to reach the hold static noise margin (HSNM). Write robustness is achieved through controlled manipulation of the inverter pull-down paths, facilitating conflict-free write operations without aggressive transistor upsizing or complex assist circuitry. HSPICE simulations using the Stanford 32-nm CNTFET model demonstrate that, at a supply voltage of 0.3&#xa0;V, the proposed SRAM achieves a 2.1 × improvement in RSNM and over a 14 × enhancement in write static noise margin (WSNM) compared to the conventional 6T SRAM. In addition, reduced bitline activity, elimination of precharge circuitry, and effective transistor stacking result in substantial reductions in read, write, and leakage power consumption. Monte Carlo simulations incorporating realistic process variations further confirm superior robustness, with the highest mean-to-standard-deviation ratios for both RSNM and WSNM among the compared designs. Layout-level evaluation shows that these benefits are achieved with only a modest area overhead relative to the 6T SRAM cell and with a smaller footprint than existing 9T and 10T alternatives. Overall, the proposed CNTFET-based 9T SRAM cell provides a well-balanced solution for low-voltage, energy-constrained, and variability-aware memory systems, making it a promising candidate for future CNTFET-based integrated circuits.</p>

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A CNTFET based process variation resilient SRAM design for stable low power and half select free operation

  • 期刊论文

  • 出版模式：

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  • 发表日期：

    2026年4月22日

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  • Shams Ul Haq,
  • Alireza Aminzadeh,
  • Abdolreza Darabi,
  • Erfan Abbasian,
  • Owais Ahmad Shah,
  • Vakkalakula Bharath Sreenivasulu

摘要

Static random-access memory (SRAM) design at nanoscale dimensions faces critical challenges arising from degraded stability, excessive power dissipation, and heightened sensitivity to process variations, particularly under low-voltage operation. To address these limitations, this paper proposes a robust and energy-efficient carbon nanotube field-effect transistor (CNTFET)-based nine-transistor (9T) SRAM cell architecture optimized for low-power applications. The proposed design employs a fully decoupled read and write structure with a single-ended access scheme, effectively eliminating read-disturb and half-select failures while enhancing overall noise immunity. Read stability is significantly improved by isolating the storage nodes from the read bitline, enabling the read static noise margin (RSNM) to reach the hold static noise margin (HSNM). Write robustness is achieved through controlled manipulation of the inverter pull-down paths, facilitating conflict-free write operations without aggressive transistor upsizing or complex assist circuitry. HSPICE simulations using the Stanford 32-nm CNTFET model demonstrate that, at a supply voltage of 0.3 V, the proposed SRAM achieves a 2.1 × improvement in RSNM and over a 14 × enhancement in write static noise margin (WSNM) compared to the conventional 6T SRAM. In addition, reduced bitline activity, elimination of precharge circuitry, and effective transistor stacking result in substantial reductions in read, write, and leakage power consumption. Monte Carlo simulations incorporating realistic process variations further confirm superior robustness, with the highest mean-to-standard-deviation ratios for both RSNM and WSNM among the compared designs. Layout-level evaluation shows that these benefits are achieved with only a modest area overhead relative to the 6T SRAM cell and with a smaller footprint than existing 9T and 10T alternatives. Overall, the proposed CNTFET-based 9T SRAM cell provides a well-balanced solution for low-voltage, energy-constrained, and variability-aware memory systems, making it a promising candidate for future CNTFET-based integrated circuits.